Pattern inspecting method

Abstract

Abstract PURPOSE:To increase accuracy of pattern inspection by providing two or more sensors that scan a pattern in two directions perpendicular to each other in parallel and judging whether continuous number of logical 0 output of each sensor is within specified limit or not. CONSTITUTION:A pattern is scanned by sensors parallel to two directions perpendiucular to each other. The number of logical 0 output A-D is supplied to subtracters 10, 12 to calculate ¦A-B¦, ¦C-D¦, and these are inputted to comparators 20, 21. When any defect is in the pattern, comparators 20, 21 satisfy the expression 1 and output logic 1 to AND gate. A-D are inputted to an upper limit comparator U and a lower limit comparator L. When there is defect that does not satisfy the expression 2, U and L output logic 0 to NAND gate 40, and the gate 40 outputs logic 1. Outputs of gates 30, 40 are inputted to AND gate 50, and when there is defect in the pattern, logic 1 is outputted from the gate 50.

Inventors

• 👤 Giichi Kakigi
• 👤 柿木　義一
• 👤 Kikuo Mita
• 👤 三田　喜久夫
• 👤 Moritoshi Ando
• 👤 護俊 安藤
• 👤 Akifumi Muto
• 👤 明文 武藤
• 👤 Kazuo Yagi
• 👤 一夫 八木

Bibliographic Details