System for inhibiting extraction of instruction and cancellig inhibition in information processor

Abstract

Abstract PURPOSE:To improve the performance, by performing the inhibition and cancellation of the inhibition of extraction of an instruction based on a readout data of control storage so as to attain freely the inhibiting and the cancellation of the inibition of an unnecessary instruction. CONSTITUTION:An instruction is read out from a storage device 1, stored in an instruction buffer register 2 or 4 and given to a pipeline control section 6 through a selectors 5. Then, the information of the control storage CS10 is read out on a phase A tag 8 and when its specific bit is ''1'', a latch circuit FF9 is set to ''1'', and when ''0'', it is sent to ''0''. An instruction control section 7 inhibits the extraction of instruction when the circuit 9 is set to ''1'', and the inhibition of instruction extraction is cancelled when the circuit 9 is set to ''0''. Thus, the inhibition of advance-fetch and the cancellation of the inhibition of the unnecessary instruction are performed freely during the execution of the instruction or in the instruction.

Inventors

• 👤 Yoshihiro Mizushima
• 👤 水島　芳宏
• 👤 Kiyosumi Sato
• 👤 佐藤　清澄

Bibliographic Details