full adder

Abstract

Abstract PURPOSE:To shorten an adding time, and to attain its high speed processing, by providing simultaneously inputs to a logical gate. CONSTITUTION:Logical gates 1-3 constituted of a CMOS transistor have all the same function, and a full adder is constituted of a these logical gates 1-3 and a logical gate 4. When input signals A, B and Ci are inputted simultaneously, their inverted outputs are obtained by invertors 5-7. These six signals are inputted to the logical gates 1-4. A sum output signal S is obtained by a delay time of 2 stages of gates by one stage of the invertor and one stage of the logical gate 1 or 2, and also a carry signal C0 is obtained in the same way by a delay time of 2 stages of gates by one stage of the invertor and one stage of the logical gate 3 or 4.

Inventors

• 👤 Masaru Uya
• 👤 宇屋　優

Bibliographic Details