← Back to Patent Explorer
JPS5948950A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of three-dimensional integrated circuit structure

Assignee: National Institute of Advanced Industrial Science and Technology
•
Filing: 1982-09-13
•
Granted: —
•
Expires: 2002-09-13
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE:To contrive accomplishment of a remarkable increase in the integration density of the subject structure by a method wherein a three-dimensional structure is formed by providing two-dimensional ICs on a temporary substrate in such a manner that they are laminated with their faces facing to each other directly. CONSTITUTION:When the circuit layer 21 of each manufactured dimensional IC structure 10 is superposed on the upper surface of the lower structure 5, it is turned inside out and a surface 7 is faced to the surface 6. According to this method, the supporting plate 11 with which a circuit layer 21 has been supported is unnecessitated now, and the physical and permanent support of the circuit layer 21 is performed by the lower structure. Accordingly, said supporting plate 11 is completely removed if necessary, and the part where the plate 11 was removed is occupied by the circuit layer 21 as a space. It is desirable from the viewpoint of space occupation percentage that all the supporting substrate is removed, but certain extent of thickness component may be left as occasion demands. After one layer has been superposed and the substrate has been removed or reduced, the turning over and the superposing process is performed on the next circuit layer in the same manner, and the procedures are repeatedly performed, thereby enabling to easily accomplish the improvement in the integration density.

Inventors

  • 👤 Yutaka Hayashi
  • 👤 豊 林
  • 👤 Toshihiro Sekikawa
  • 👤 敏弘 関川
  • 👤 Seijirou Furukawa
  • 👤 古川 静二郎

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-26 09:50
CPC Classifications
H; H10; H10D; H10D88/00; H10W; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

JPS5893345A Cited

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag