Manufacture of complementary semiconductor device

Abstract

Abstract PURPOSE:To eliminate parasitic capacitance caused by overlap and attain the high speed, by a method wherein an insulation film having width corresponding to lateral diffusion length of impurity to be ion-implanted is formed to end at gate electrode side on active region to be ion-implanted. CONSTITUTION:When As<+> ion is implanted in P type well region 22, a first remaining CVD-SiO2 film 28 having width equal to lateral diffusion length LA of arsenic is formed to end at side of a gate electrode 272, thereby the gate electrode 272 and N<+> type source and drain regions 30, 31 are not overlapped. When B<+> ion is implanted in N type silicon substrate 21, first and second remaining CVD-SiO2 films 28', 32' having width equal to lateral diffusion length LB are formed to end at side of a gate electrode 271, thereby the gate electrode 271 and P<+> type source and drain regions 34, 35 are not overlapped.

Inventors

• 👤 Yoji Yasuda
• 👤 安田　洋史
• 👤 Hiroshi Nozawa
• 👤 野沢　博
• 👤 Kazuhiko Hashimoto
• 👤 一彦 橋本

Bibliographic Details