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JPS5936942A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor integrated circuit

Assignee: Toshiba Corp
•
Filing: 1982-08-25
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Granted: —
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Expires: 2002-08-25
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Abstract

Abstract PURPOSE:To remarkably enlarge the range of the automatic arrangement wiring program by a method wherein wiring channels are arranged between lines of unit cells in addition to the wiring channels arranged between each row of conventional unit cells. CONSTITUTION:The unit cells 11 are regularaly arranged in matrix form, and the wiring channels 12 are provided between each row of these cells 11. A wiring channel 13 is provided to the direction rectangular to the wirings 12 between lines of every fixed number of the unit cells 11. It follows that a chip laid out by two-step method contains cells in the sum of the number contained in each block, and accordingly the limitation that the automatic arrangement wiring program has can be practically eliminated.

Inventors

  • 👤 Yuko Ogawa
  • 👤 小川 祐子

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-23 11:42
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90

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