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JPS59229656A Expired / Lapsed JP ⏱️ 0.0 years remaining

Debugging device of program

Assignee: Fuji Electric Co Ltd
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Filing: 1983-06-13
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Granted: —
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Expires: 2003-06-13
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Abstract

Abstract PURPOSE:To improve the efficiency of debugging work by adding an execution address itself to an instruction word which is not in a direct address format, and noticing directly the execution state of a program. CONSTITUTION:A CPU11 reads out an instruction from a memory 13 and transmits/receives data to/from I/O device through a bus 14. The instruction is read out from the memory 13 and executed by the CPU11. When the instruction is not a direct address format, an execution address for operating a prescribed I/O 12 or the like is outputted, the succeeding instruction work is read out and hereinafter prescribed processing is executed. In the debugging device 2, information outputted to the bus 14 is read out and decoded by an instruction decoding part 21, and if the information is an instruction word, the information is sequentially stored in an instruction trace buffer 22. A display part 24 displays the execution state of the instruction as the format of a direct address instruction.

Inventors

  • 👤 Toyohiro Nakanouchi
  • 👤 中野内 豊広

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 20:45
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36

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