Control circuit of dynamic ram

Abstract

Abstract PURPOSE:To simplify the constitution of a peripheral circuit and to reduce whole size by enabling a dynamic RAM having a refresh function to execute a refresh operation automatically. CONSTITUTION:In a reading-out mode, an FF43 is set up synchronously with a WR signal corresponding to an instruction D1, the RAS terminal of a RAM12 is turned to ''1'' and the line signal of an address signal is inputted to the RAM12. When a CAS is turned to ''1'' accordance with an instruction D2, a row signal is inputted to the RAM12, and simultaneously, reading-out data are moved from the RAM12 to a CPU11 and outputted. During said period, the output terminal of an AND circuit 46 is ''0'' and the refresh terminal RF of the RAM12 is also ''0'', so that the refresh operation is not executed. The output terminal of the FF43 and the RAS terminal are turned to ''0'' by the WR signal corresponding to D3 and the address signal is unlatched. At that time, the AND circuit 46 passes an RD signal and a refresh signal corresponding to the RD signal is applied to the terminal RF to refresh the RAM12.

Inventors

• 👤 Masayuki Kuroki
• 👤 正幸 黒木

Bibliographic Details