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JPS59169166A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Hitachi Ltd
•
Filing: 1983-03-16
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Granted: —
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Expires: 2003-03-16
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Abstract

Abstract PURPOSE:To improve the input and internal characteristics of a semiconductor device by providing two power lines for an output circuit and for input and internal circuits, and interposing a buffer circuit between the both circuits, thereby preventing the increase in the level of the input and internal circuits due to simultaneous ON operations of a plurality of output circuits. CONSTITUTION:Only the output circuit 16 of an I/O buffer 13 is connected to a power line 19 connected to a GND pad 18, and an input circuit 15 and an internal circuit 12 are connected to a power line 20. An integrated circuit is formed of a capacitor 22 formed of floating capacity between the line 20 and a chip substrate, and a resistor 21 connected to the lines 19, 20, and interposed as a buffer circuit 23 between the lines 19 and 20. When a plurality of output circuits 16 are simultaneously turned ON, a noise is generated at the pad 18, i.e., the line 19, and even if the level is raised in a peak manner, the integrating operation in the buffer circuit 23 or the voltage dropping operation due to the resistor 21 is acted on the line 20, and the raised level is not transmitted as it is.

Inventors

  • 👤 Kanji Yo
  • 👤 陽 完治

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 01:53
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90

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Total Claims: 0
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