Semiconductor logical circuit device

Abstract

Abstract PURPOSE:To largely reduce the write time of an ROM by enabling the write of contents in the ROM device by the addition of the process of injecting the same conductivity type impurity as source and drain regions. CONSTITUTION:The part of a gate insulation layer 181 is implanted the same conductivity type impurity as that of source region 15 and drain region 16, i.e., P type impurity, and the surface of an Si substrate 11 is doped with the P type impurity, resulting in the formation of P<+> type impurity regions, i.e., the first impurity regions 24 and 25 respectively. Since these regions 24 and 25 work as a part of the source region 15 and drain region 16, an actual working IGFET is constituted. On the other hand, the part of a gate insulation layer 182 is implanted the reverse conductivity type impurity to that of the source region 15 and drain region 16, i.e., N type impurity, and the surface of the Si substrate 11 is doped with the N type impurity, resulting in the formation of N type impurity regions, i.e., the second impurity regions 26 and 27 respectively. Since these regions 26 and 27 have N conductivity type which is reverse to that of the source region 15 and drain regions 16, only non working IGFET is constituted.

Inventors

• 👤 Yasoji Suzuki
• 👤 八十二 鈴木
• 👤 Kenji Manabe
• 👤 真鍋　研司

Bibliographic Details