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JPS5895271A Expired / Lapsed JP ⏱️ 0.0 years remaining

Testing device for semiconductor integrated circuit

Assignee: NEC Corp
•
Filing: 1981-12-01
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Granted: —
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Expires: 2001-12-01
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Abstract

Abstract PURPOSE:To automatically and precisely detect marking setting errors by simultaneously testing plural elements to be tested and, when tested result is inconsistent in spite of the retrial of test when accepted and rejected results are mixed, stopping the operation of an IC tester. CONSTITUTION:Plural, 2 paris e.g., elements 31, 32 to be tested in a wafer 3 are simultaneously tested by a measuring circuit 11 in an IC testor 1, and when accepted and rejected results are mixed, these results are stored in a storing and measuring circuit 25 in a wafer prober. When tested results are inconsistent each other even if the test is retired through a control circuit 21 in the prober 2 and the circuit 12, an inhibiting circuit 26 keeps its inhibiting status through a discrimination output from the circuit 25, so that the movement of the wafer 3 by prober 2 is inhibited and an alarm is generated to stop the operation of the testor 1. Thus marking setting errors by markers 22, 23 are automatically and precisely detected, inhibiting the loss accumulation due to incorrect tests.

Inventors

  • 👤 Hideo Ishiguro
  • 👤 石黒 秀男

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-29 07:48
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/316

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