Mos dynamic memory

Abstract

Abstract PURPOSE:To reduce fluctuation of memory voltage and enable high speed action by providing a variable impedance device and a decoupling capacitance between a power source terminal and a base plate of memory cell. CONSTITUTION:A variable impedance device 28 and a decoupling capacity 30 are provided between a power source line and a base plate of memory cell and the connecting point is made a node 31. In this case, a memory capacity is used as capacitance 30. At a time t2 of reading, a signal phi is low level. As the node 30 is floated, and the capacitance 30 is separated, and the capacitance Css between the base plate and Vss is made small, fluctuation of base plate potential VBB becomes larger and the capacitance between common latch node and Vss becomes smaller. Thus, it becomes suitable for high speed action. When the signal phi is made high level, the node 31 is recharged to external power source level, and gives positive change to potential VBB level through the capacitance 30. Thereafter, the word line becomes low level and writing of H level and L level is made to the memory cell. Accordingly, fluctuation of voltage caused by fluctuation of potential VBB can be reduced.

Inventors

• 👤 Kazuyasu Fujishima
• 👤 一康 藤島

Bibliographic Details