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JPS5892005A Expired / Lapsed JP ⏱️ 0.0 years remaining

Programmable controller

Assignee: Omron Corp
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Filing: 1981-11-26
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Granted: —
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Expires: 2001-11-26
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Abstract

Abstract PURPOSE:To improve the processing speed, by arranging input/output devices and memories on the same bus line, assigning the address to the same and controlling the memories through a signal representing the types of input and output cards as a gate. CONSTITUTION:An internal memory 5 is connected to a common bus line 7 to which input/output racks 6-1, 6-2 are connected and the same addresses are assigned to each rack. Further, input or output cards 9, 10 are incoporated with card discriminating circuits 8-1, 8-2 outputting a discriminating signal representing the input or output of the card in response to the address designation opration to the said cards. That is, at output, the same data are written in the memory 5 and input/output devices and when the input card 9 exists at input, the memory 5 is inhibited and only the content of the input card 9 is read. When the input card 9 does not exist or the output card 10 exists, the content of the memory 5 is read, allowing to save useless time for input and output control and to attain high speed processing.

Inventors

  • 👤 Minoru Ogawa
  • 👤 実 小川

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-25 15:40
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/05; G05B19/054; G05B2219/00; G05B2219/10; G05B2219/11; G05B2219/1188

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS5474090A Cited

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