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JPS5890853A Expired / Lapsed JP ⏱️ 0.0 years remaining

Input detection circuit

Assignee: Toshiba Corp
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Filing: 1981-11-26
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Granted: —
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Expires: 2001-11-26
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Abstract

Abstract PURPOSE:To increase the amount of information of input signals and to provide a new function to a digital system, by providing an intemediate level state in addition to high and low level states, and detecting also the intermediate level state. CONSTITUTION:An input signal In is given to a logical circuit 13 through two inverting type input buffer circuits 11, 12 having different threshold voltage state. The logical circuit 13 performs a prescribed logical operation. When the levels of the input signal In are VDD-VIH1, levels of low; high; high are obtained at outputs A, B, C of the circuit 13, and when the levels of the In are intermediate level of VIL1-VIH2, and VIL2-GND, high; high; low and high; low; high levels are obtained at the outputs A, B, C, allowing to discriminate the high; intemediate; low, three levels of the input signal In.

Inventors

  • 👤 Makinari Kobayashi
  • 👤 小林 万企就

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 11:29
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/06

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