Insulating gate type field-effect transistor

Abstract

Abstract PURPOSE:To enable to connect a gate electrode and a wiring on a channel region even when a displacement is generated in mask-matching by a method wherein a gate electrode is formed using a laminated film, the upper layer located above said electrode is composed of the film having the etching speed slower than that of an interlayer insulating film, and said upper layer film is squeezed out with sufficient width on the source and the drain regions. CONSTITUTION:A gate insulating layer 1, as a gate insulating film, is composed of a two-layer structure consisting of an SiO2 film 2 and an Si3N4 film 3, and said layer is squeezed out in sufficient width on an N<+> type source region 4 and the drain region 5. A through hole 8, to be used to connect an aluminum wiring 7 to the gate electrode 6, is formed on the interlayer insulating film (a phosphor-silicate glass film) 9 on a region located in a channel width W. According to the above constitution even, when the through-hole 8 is deviated to the side of the source region 4 due to the displacement of mask-matching, the short-circuit generating between the aluminum wiring 7 and the source region 4 can be effectively prevented because there exists the Si3N4 film 3 and the SiO2 film 2. Accordingly, as the gate electrode 6 and the aluminum wiring 7 can be connected to the gate electrode, the area required for said connection can be greatly reduced as compared with that required for the connection which will be performed on the field SiO2 film, thereby enabling to form a highly integrated IC.

Inventors

• 👤 Yoshiaki Onishi
• 👤 良明 大西

Bibliographic Details