Mos type transfer gate circuit

Abstract

Abstract PURPOSE:To surely attain a high speed operation with a comparatively simple circuit constitution, by providing a buffer circuit for a gate of a signal controlling transistor (TR). CONSTITUTION:A gate circuit of signal controlling MOSFETQ2 is provided with a mitigation circuit 13. A node F is charged to a power supply voltage V when signals phi1 and phi2 are at ''0'' level, and the TRQ2 is set on. When the signal phi2 rises to ''1'' level, the node F is boosted with a capacitor between the drain and gate of the FETQ2, the conductive resistance of the FETQ2 is decreased, and the node A is rapidly charged. The mitigation circuit 13 restores the boosted potential at the node F to the power supply voltage V after a prescribed time, and since the voltage between the drain and source of the FETQ2 is at high level, the FETQ2 is turned off, and when the signal phi1 rises, the potential of the node A pulled up is kept. Since the FETQ1 can be controlled for conduction with a pulled-up high voltage, the leading of a node B can be quickened.

Inventors

• 👤 Hidetake Fujii
• 👤 藤井　秀壮

Bibliographic Details