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JPS5879338A Expired / Lapsed JP ⏱️ 0.0 years remaining

Logical circuit

Assignee: Toshiba Corp
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Filing: 1981-11-05
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Granted: —
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Expires: 2001-11-05
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Abstract

Abstract PURPOSE:To realize a high speed, through the reduction in the settling time after precharge, by precharging a connecting point between a dynamic type logical circuit consisting of C-MOSs and an input circuit, with a precharge signal. CONSTITUTION:While a precharge signal phip is 0 level in case of a tri-state input logical product circuit, an MOS transitor (TR) MOSU is conductive and either one of MOS TRs MOS1-3 is nonconductive, a capacitor CL is precharged to the level of a power supply VDD and an output signal VOUT is 1 level. When all input signals go to 1, the TRs MOS1-3 are all conductive, a voltage at nodes N1-3 is low and amount of charges stored at each node is less. Then, even if the precharge signal phip changes from 0 to 1 and the TR MOSU changes into nonconductive, the charges in the capacitor CL and at each node are discharged to ground immediately, and the settling time of the output signal VOUT is short, allowing to attain high speed.

Inventors

  • 👤 Hideji Koike
  • 👤 秀治 小池

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 18:55
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01728

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