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JPS5877351A Expired / Lapsed JP ⏱️ 0.0 years remaining

Packet buffer congestion monitor system

Assignee: NTT Inc
•
Filing: 1981-11-04
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Granted: —
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Expires: 2001-11-04
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Abstract

Abstract PURPOSE:To enable a CPU to detect the congestion of packet buffer early, by providing a buffer congestion monitor section for a CCE (communication controller) for the self-monitor and information. CONSTITUTION:A CPU 1 informs a number of use of buffer to a buffer congestion monitor section 5 via a block transfer control section 4 and stores the value to a memory in the section 5. When the section 5 detects that the number of buffer usage reaches a prescribed value or over, the section 5 requests the information of the buffer congestion to the CPU 1 for the section 4. When the CPU 1 receives interruption from a CCE2 and the information of buffer congestion, the CPU 1 gives instruction of the information of the number of buffer usage. The section 4 follows the instruction, receives the report of the number of buffer usage from the buffer congestion monitor section 5 and informs the CPU 1 of it. The CPU 1 checks whether or not the number of usage exceeds a prescribed number every time the information is received and if the CPU 1 exceeds continuously for a prescribed number of times, the input restriction packet is transmitted.

Inventors

  • 👤 Yoshiaki Yomo
  • 👤 四方 義昭
  • 👤 Kinzaburo Yoshie
  • 👤 吉江 金三郎
  • 👤 Iwao Takagi
  • 👤 高木 岩生

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-25 09:53
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802

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