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JPS5877251A Expired / Lapsed JP ⏱️ 0.0 years remaining

Ic package

Assignee: NEC Corp
•
Filing: 1981-11-02
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Granted: —
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Expires: 2001-11-02
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Abstract

Abstract PURPOSE:To erase actually the effect of inductance at a lead part, and to remove voltage variation of an electric power source terminal according to the action of an LSI itself by a method wherein a capacitor is built in according to a proper method between stitches for electric power source terminal and for earthing in a package. CONSTITUTION:A chip type capacitor 4 is provided between an electric power source pad VDD and an earthing pad VSS, and electrodes of the capacitor 4 and stitches of a package are connected with solder 5. Although an electric power source current varies as usual according to action of an LSI 6 itself, it is absorbed by the capacitor 4, and variation of current to appear in inductance becomes to extremely small. Accordingly, voltage variation to appear between electric power source terminals of LSI chip becomes small, and stable action can be attained.

Inventors

  • 👤 Yoshio Kachi
  • 👤 加地 善男

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 23:46
CPC Classifications
H; H10; H10W; H10W44/00; H10W44/601; H10W72/00; H10W72/071; H10W72/075; H10W72/07551; H10W72/50

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