Signal reception circuit

Abstract

Abstract PURPOSE:To decrease the code error rate, by measuring the level of a detection signal with two frequencies provided at the pre-stage of an FS data signal, selecting an inverting characteristic filter through the ratio, and compensating the unbalancing of the FS data signal. CONSTITUTION:Detection signal of two frequencies added prior to an FS data signal are inputted to an AC/DC conversion circuit 15 via a BPF 11, A signal detection circuit 16 produces an output when the converted DC signal is a prescribed value or over and gives a start signal to a microprocessor 18. The processor 18 stores the detection signal outputted from an A/D conversion circuit 17, operates the ratio of the amplitude of both the signal and gives a control output to an unbalance compensation circuit 14. The circuit 14 consists of a filter, the characteristic of which can be switched, so that both the detection signals are balanced with the output of the processor 18.

Inventors

• 👤 Shigeru Tanaka
• 👤 茂 田中
• 👤 Morikazu Ikeda
• 👤 池田　守一
• 👤 Toyohisa Takahata
• 👤 高畑　豊寿
• 👤 Naoki Kawarada
• 👤 河原田　直樹
• 👤 Terutomo Kobayashi
• 👤 小林　照朋
• 👤 Yoshinori Okiishi
• 👤 沖石　良憲
• 👤 Takao Yoshihara
• 👤 吉原　孝夫
• 👤 Masayoshi Kawaguchi
• 👤 川口　真由

Bibliographic Details