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JPS5872073A Expired / Lapsed JP ⏱️ 0.0 years remaining

Cycle synchronizing system for loran c receiving pulse

Assignee: Fujitsu Ltd
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Filing: 1981-10-27
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Granted: —
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Expires: 2001-10-27
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Abstract

Abstract PURPOSE:To measure accurately a voltage ratio of the peak part even if S/N is degraded, by extending equivalently dynamic ranges of a sample holding circuit and an A/D converter which measure the peak value of a loran C receiving pulse. CONSTITUTION:A pulse generating circuit 3 generates sampling pulses of a certain period in accordance with respective parts of peaks of loral C pulses, and the first and the second constant voltage generating circuits 8 and 9 generate constant voltage pulses 10 and 11 respectively by these sampling pulses. These constant voltage pulses are added to the output from an amplifier 1 in a successive adding circuit 7. A sample holding circuit 2 samples and holds the synthetic output by sample holding pulses from the pulse generating circit 3, and the sample value is converted to a digital value by an A/D converter 4. A CPU 6 obtains a ratio of digital values corresponding to two continuous peaks on a basis of the digital value outputted from the A/D converter 4 to discriminate the third cycle, and phase matching is performed by the discrimination result.

Inventors

  • 👤 Hiroshi Horikawa
  • 👤 博 堀川

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 12:24
CPC Classifications
G; G01; G01S; G01S1/00; G01S1/02; G01S1/08; G01S1/20; G01S1/24; G01S1/245

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