← Back to Patent Explorer
JPS5853845A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor integrated circuit

Assignee: Fujitsu Ltd
•
Filing: 1981-09-26
•
Granted: —
•
Expires: 2001-09-26
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE:To remove the coupling capacity, by providing ohmic electrodes grounded between semiconductor elements or circuits on a semi-insulating or insulating substrate. CONSTITUTION:N channel regions 4a, 4b and N<+> sources 2a, 2b and N<+> drains 3a, 3b on both sides thereof are formed on the semi-insulating GaAs substrate 1 by a conventional method. Schottky gate electrodes 5a, 5b of Ti/W silicides are provided on the channel, and ohmic electrodes 6a, 6b, 7a, 7b of AuGe/Au, etc. are provided on the source and drain. Further, the substrate is covered with an SiO2 8, windows are opened 9, and then Ti/Pt/Au upper layer wirings 10 of ohmic connection are provided. When the band formed N layer 11 ohmic-connected to the band formed grounding electrode 12 is formed between these FETs shielded, the both elements are perfectly isolated against high freqency resulting in the prevention of error operations due to signal leak.

Inventors

  • 👤 Katsuhiko Suyama
  • 👤 須山 勝彦

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 10:25
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

JPS492437A Cited
JPS5074980A Cited

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag