semiconductor equipment

Abstract

Abstract PURPOSE:To obtain a lateral transistor available for the free trimming of the control of amplification factors and emitter dimensions, by controlling emitter currents by voltage impression onto a gate electrode. CONSTITUTION:Since a P type inversed layer 5 is generated on the surface of an N<-> type Si substrate 1 under the gate by impressing a voltage onto the gate G and the area of a P<+> type emitter 3 increases resulting in the reduction of a substantial base width WB, and thereby the amplification factor hFE of the lateral P-N-P transistor fluctuates by the gate voltage VG. Further, a plurality of P<+> type emitters 3a, 3b are provided on the surface of an N<-> layer 9, the gate G is provided on the surface of the N<-> layer (base) between emitters via insulating films 4, the emitter area (peripheral length) is substantially increased by the P type inverted layer 5 generated by impressing a negative voltage onto the gate, and emitter currents are varied resulting in the fluctuation of the hFE. Thus, by providing an insulating gate electrode on the base and impressing a voltage thereon, the base width is varied resulting in the control of the hFE, and the N<-> layer is formed on the base surface resulting in the control of the hFE. Further, collector currents are varied by making the emitter area and the peripheral length variable, and thereby programmable elements or elements available for trimming can be obtained.

Inventors

• 👤 Toshiaki Matsubara
• 👤 松原　俊明

Bibliographic Details