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JPS5846709A Expired / Lapsed JP ⏱️ 0.0 years remaining

Level blanking circuit

Assignee: Anritsu Corp
•
Filing: 1981-09-14
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Granted: —
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Expires: 2001-09-14
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Abstract

Abstract PURPOSE:To prevent the occurrence of the impulsive noise, by providing two gain varying circuits to ensure the smooth switching of signals. CONSTITUTION:The output signal given from a oscillator 1 is delivered from a terminal 6 via a switching circuit. When the signal level of the oscillator 1 is changed, a changeover switch SW is switched to a voltage generator 10b. An operational amplifier OP1 constitutes a Miller integration circuit, and the output voltage of the amplifier OP1 drops with the prescribed time. With this drop of voltage, the degree of attenuation of the 1st gain varying circuit increases. When this degree of attenuation reaches the highest level, the output of an operational amplifier OP2 in a level shifting circuit 12 is inverted. Then the 2nd gain varying circuit works to further increase the degree of attenuation. When the output is set at 0, a relay 5 works to switch the SW. Thus the degree of attenuation of the gain varying circuit is reduced. At the same time, the output level is changed.

Inventors

  • 👤 Hideo Mori
  • 👤 秀夫 森
  • 👤 Masayuki Uragami
  • 👤 浦上 正行
  • 👤 Minoru Nomoto
  • 👤 野本 実

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 17:12
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/34; H03G3/345

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