Integrated structure of high voltage complementary mos inverter array

Abstract

Abstract PURPOSE:To obtain inexpensively an inverter array by integrating a circuit which is formed of a load side transistor, a shunt resistor and a diode on a semiconductor substrate and a circuit which is formed of a drive side transistor, a shunt resistor, a diode and a gate input condenser, and connecting them by external wirings. CONSTITUTION:Four high withstand voltage PMOS transistor circuits having integrated high resistors and a diode between a gate electrode and a source electrode on an N type semiconductor substrate as an integrated circuit element 19. Four integrated high withstand voltage NMOS transistor circuits are formed on a P type semiconductor substrate as an integrated circuit element 29, and the elements 19, 29 are connected to each other. In other words, the gate terminals 11, 13, 15, 17 of the element 19 are respectively connected via external wirings to the gate input condenser terminals 21, 23, 25, 27 of the element 29. The drain terminals 12, 14, 16, 18 of the element 19 are respectively connected by external wirings similarly to the drain terminals 22, 24, 26, 28 of the element 29.

Inventors

• 👤 Hiroshi Sakuma
• 👤 啓 佐久間

Bibliographic Details