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JPS584449A Expired / Lapsed JP ⏱️ 0.0 years remaining

Instruction buffer control system

Assignee: Fujitsu Ltd
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Filing: 1981-06-30
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Granted: —
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Expires: 2001-06-30
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Abstract

Abstract PURPOSE:To reduce the number of registers which store the pre-fetched instruction groups, by selecting one unit out of a gathering comprising a current register, a target register and an instruction buffer register and then feeding an instruction to a pipeline control part. CONSTITUTION:A current register 11 loads the instruction word data read out of a storage part. A target register 10 loads the instruction word data read out of a main storage part. A selector 14 selects a unit out of a gathering comprising the register 11 and the register 10. The contents of the register selected by the selector 14 is loaded to an instruction buffer register 12. A selector 15 selects a unit out of the group comprising the registers 11, 10 and 12, and the instruction of the selected register is fed to a pipeline control part 13.

Inventors

  • 👤 Yoshihiro Mizushima
  • 👤 水島 芳宏
  • 👤 Kazuyuki Shimizu
  • 👤 和之 清水

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 19:15
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS5039437A Cited
JPS5282149A Cited

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