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JPS5840618A Expired / Lapsed JP ⏱️ 0.0 years remaining

Process input/output control method

Assignee: Hitachi Ltd
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Filing: 1982-01-11
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Granted: —
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Expires: 2002-01-11
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Abstract

Abstract PURPOSE:To control a process input and output signal without laying a large load on a computer for control, by putting a processor, dedicated to process input and output, in charge of the input and output processing of processes and the editing of data. CONSTITUTION:A processor PIOP3 dedicated to process input and output refers to a table for data conversion stored in its private core 4 to edit input data, and then writes the edited data in linkage buffers 18 and 20 in such a way that a host computer processes them easily. On the writing to the linkage buffers 18 and 20, the PIOP displays PIOP occupation on fetch display registers 17 and 19, and output interruption signals 12 and 13 for commanding the host computer to fetch the data in the linkage buffers. The host computer once receiving said interruption signals 12 and 13 fetches the data in the linkage buffers 18 and 20 to perform data processing. After the processing, the fetch display registers 17 and 19 change in display to show the fetch operation is completed.

Inventors

  • 👤 Kazuo Kaira
  • 👤 和郎 解良
  • 👤 Koichi Ihara
  • 👤 廣一 井原
  • 👤 Yutaka Kubo
  • 👤 裕 久保

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 19:33
CPC Classifications
G; G05; G05B; G05B15/00; G05B15/02

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