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JPS582946A Expired / Lapsed JP ⏱️ 0.0 years remaining

Memory extending substitution system

Assignee: Toshiba Corp
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Filing: 1981-06-30
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Granted: —
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Expires: 2001-06-30
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Abstract

Abstract PURPOSE:To substitute a storage part for a faulty ROM easily, by adding the read address of the ROM to the address difference between a specific instruction address of the ROM and its substitutional instruction address to call a substitutional instruction and making instructions from the ROM ineffective. CONSTITUTION:Substitutional instructions for instructions in specific addresses of a ROM1 where controlling micro mu programs are stored are stored in a memory WCS3. When information of a specific address is sent from a mu program sequencer MPS2 to the ROM1, the instruction in this address is read out from the ROM1 and is stored in a mu instruction register 12. Simultaneously, this address information is read out and is decoded in a substitution indicating part 5 to send an indicating signal 6 to an address difference information holding register part 4. The register 4 sends information of the address difference between the held specific address of the ROM1 and the address of the substitutional insturction of the WCS3 to an adding circuit 9, and the substitutional instruction of the WCS3 is read out by an address obtained by adding this address difference and the address from the MPS2. An instruction discrimination controlling circuit 13 makes instructions from the ROM1 ineffective by an instruction inhibiting signal 8 from the indicating part 5 to execute substitutional instructions from the WCS 3.

Inventors

  • 👤 Rikiyoshi Takahashi
  • 👤 高橋 力良

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 11:30
CPC Classifications
G; G06; G06F; G06F8/00; G06F8/60; G06F8/65; G06F8/66; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F9/322; G06F9/328

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