Low speed memory access control system

Abstract

Abstract PURPOSE:To improve the efficiency of use of a central processing unit, by suitably changing an instruction execution control so that no vacant time can be formed for the operation of the central processing unit in the process executing an instruction group with comparatively longer access time. CONSTITUTION:When a high speed memory access instruction and a common memory device (CM) access instruction are executed, a central processing unit CP010 moves the instruction execution control to the execution of an instruction not including the CM access when the memory access corresponds to the CM50. When the CM access request is received, the CM50 stores the request to a holding circuit 501. The operation of the CP010 to the request is started and before the CM operation is completely finished, a CM operation completion forecast signal is transmitted to the CP010 from a CM control circuit 503. On the other hand, when the CP010 receives this forecast signal, the control of execution of the instruction is restored to the post-processing of the original CM access instruction and a response signal transmitted from the CM after a prescribed time from this forecast signal is fetched to a receiver circuit 102. When all the operations are finished, the instruction execution control is moved to the next instruction again.

Inventors

• 👤 Tooru Asatsu
• 👤 朝津　徹

Bibliographic Details