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JPS582073A Expired / Lapsed JP ⏱️ 0.0 years remaining

Field effect transistor

Assignee: Sony Corp
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Filing: 1981-06-29
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Granted: —
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Expires: 2001-06-29
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Abstract

Abstract PURPOSE:To obtain easily an MOSFET processed at a low temperature using amorphous silicon by a mthod wherein the amorphous region is formed between a source and a drain, and a gate is formed insulatedly on a semiconductor layer between the source and the drain. CONSTITUTION:The amorphous silicon layer 2 is formed on a substrate 1 of which the surface is an insulator, a glass substrate for example, using the plasma CVD method. A gate insulating film 3 and insulating layers 4 are formed on the amorphous silicon layer 2, and openings 5, 6 are formed. Then the gate electrode 7 is formed on the gate insulating film 3, and moreover ion implantation and selective annealing are performed through the openings 5, 6 to form the source region 8 and the drain region 9. The source and drain regions 8, 9 are converted into the minute polycrystalline regions by selective annealing thereof, and the channel part 13 remains as the amorphous region. Then a source electrode 10 and a drain electrode 11 are formed in the source and drain regions 8, 9.

Inventors

  • 👤 Hisao Hayashi
  • 👤 久雄 林
  • 👤 Masanori Noda
  • 👤 昌敬 野田

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 18:13
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60

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