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JPS58200554A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor device

Assignee: Hitachi Ltd
•
Filing: 1982-05-19
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Granted: —
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Expires: 2002-05-19
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Abstract

Abstract PURPOSE:To form a dielectric, and to reduce wiring capacitance in an element isolation region by implanting a substance, which combines with silicon and forms the dielectric, in a semiconductor substrate through an ion implantation method. CONSTITUTION:An element isolation groove is formed to the P type Si substrate 1 to which an N<+> buried diffusion layer 2 and an epitaxial growth layer 3 are formed, an SiO2 film 6 is deposited, the surface of the epitaxial layer 3 is exposed through etching, oxygen is injected only into the element isolation region 4 through ion implantation while using a resist pattern 7 as a mask, and silicon oxide 8 is formed. The resist pattern 7 is removed, and an element is formed through a conventional method. Capacitance between wiring 12 and the substrate 1 can be reduced effectively by increasing the energy of ion implantation and implanting oxygen up to a deep section. Nitrogen, etc. may be used as an the substances to be implanted.

Inventors

  • 👤 Takeo Shiba
  • 👤 健夫 芝
  • 👤 Yoichi Tamaoki
  • 👤 玉置 洋一

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 17:43
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/10

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