Tri-state logical circuit

Abstract

Abstract PURPOSE:To decrease the occupying area of a cell, by connecting a parallel circuit of two P channel MOS transistors (TRs), and that of P channel MOS TR and two N channel MOS TRs in series. CONSTITUTION:When a disable input I9 is at an L level, a gate input of TRs 8 and 19 goes to an H level, a TR8 is turned off, a TR19 is turned on and a TR18 is turned off. When a data input I8 is at the L level, a TR7 is turned on, and a TR17 is turned off. Thus, a gate input of a P channel MOS TR9 of output TRs goes to the H level to be off. An N channel MOS TR20 is turned on and an output O5 goes to the L level. When the data input I8 goes to the H level, the output state goes to the H level. Further, when the disable input I9 goes to the H level, the output O5 has a high impedance independently of the level of the data input I8.

Inventors

• 👤 Fusao Tsubokura
• 👤 坪倉　富左雄

Bibliographic Details