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JPS58154263A Expired / Lapsed JP ⏱️ 0.0 years remaining

Hall integrated circuit

Assignee: Seiko Instruments Inc
•
Filing: 1982-03-09
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Granted: —
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Expires: 2002-03-09
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Abstract

Abstract PURPOSE:To prevent the variation of Hall voltage due to distortion voltage by a method wherein the distortion voltage generated between Hall electrodes of Hall elements is erased by the distortion generated on the substrate of a Hall IC. CONSTITUTION:Two Hall elements 11 and 21 on the same substrate are arranged so as to make the direction of flowing current in reverse directions. When the distortions applied on the elements 11 and 21 are the same, electrodes 15 and 25 are connected each other, so that the distortion voltage generated in the Hall electrodes 14 and 15 of the element 11 is erased each other with the distortion voltage generated in the Hall electrodes 24 and 25 of the element 21, and accordingly the output from the electrodes 14 and 24 is inputted into an amplifier 6. Therefore, the off-set voltage due to the distortion voltage does not appear on output terminals. On the other hand, since the Hall voltage due to a magnetic field 13 is outputted in the direction wherein two Hall voltages are added, the Hall voltage with extremely small influences due to distortions can be taken out.

Inventors

  • 👤 Masaaki Kamiya
  • 👤 昌明 神谷

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 11:40
CPC Classifications
H; H10; H10B; H10B61/00; H10N; H10N59/00

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS55125688A Cited

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