Field effect transistor logic circuit

Abstract

Abstract PURPOSE:To attain high speed, low power consumption and stable operation, by connecting a current source to a terminal to which source terminals of input stage of a field effect transistors of two inverters are connected in common. CONSTITUTION:A source 11 connecting sources of FETs 1, 2, 3-5 in common is connected to a source power supply voltage terminal VSS via a constant current source 12. A load 13 is connected to a power supply voltage terminal VDD and a drain of the FET1 is connected to the VDD via a load 14. To the gate of FETs 15, 16 in which the source is connected to the VSS via diodes 17, 18 and resistors 19, 20 and the drain is connected to the VDD, the drains of the FETs 1-5, to pick up an NOR output of the input to the FETs 2-5 from a connecting point F1 between the diode 17 and the resistor 19 and an OR output from a connecting point F2 between the diode 18 and the resistor 20.

Inventors

• 👤 Shinichi Katsu
• 👤 勝　新一
• 👤 Akio Shimano
• 👤 嶋野　彰夫
• 👤 Shutaro Nanbu
• 👤 修太郎 南部

Bibliographic Details