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JPS58115995A Expired / Lapsed JP ⏱️ 0.0 years remaining

Signal processing circuit

Assignee: Sony Corp
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Filing: 1981-12-29
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Granted: —
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Expires: 2001-12-29
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Abstract

Abstract PURPOSE:To effectively use a frame memory, by using a frame memory, the detection of movement and a control circuit in common for the realization of both Y/C separation and noise reduction, relating to a signal processing circuit separating a luminance and a chroma signal (Y/C separation) from a composite color television signal. CONSTITUTION:A signal delayed by TF, being the subtraction of the sum of a delay time T1 of a band pass filter 22 and a delay time T2 of a two-dimension comb type filter 23, (T1+T2) from one frame TF, is picked up from a 1-frame memory 4, applied to a delay circuit 28 and the filter 22, a signal F2 is formed with synthesizers 30, 32 and a chroma inverter 31, and the signal F2 is applied to a movement detection and control circuit 17 together with the signals F3, F1. The signals F1, F2, F3 are applied to a synthesizer 11 via multipliers 5, 6 and 7 respectively and a gate circuit 36, and the gate circuit 36 is controlled, allowing to attain the Y/C separation.

Inventors

  • 👤 Yoshitaka Hashimoto
  • 👤 橋本 慶隆
  • 👤 Seiichiro Iwase
  • 👤 岩瀬 清一郎

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-25 00:29
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/77; H04N9/78

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