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JPS5790971A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory storage and its manufacture

Assignee: Toshiba Corp
•
Filing: 1980-11-27
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Granted: —
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Expires: 2000-11-27
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Abstract

Abstract PURPOSE:To prepare the device, which is integrated to a high degree and has a large margin, in high yield by a method wherein a material layer, the speed of oxidation thereof is faster than a substrate, is oxidized selectively and used as a separation region, and a capacity electrode is formed in a shape that is contacted with an end section of a side surface of a separation oxide layer and folded. CONSTITUTION:The layer such as a phosphorus doped poly Si layer 23 is deposited on the P type substrate 31 through an oxide film 22, a nitride film mask 24 is shaped in an element forming region, and P<+> channel stopping layers 25 are injected and formed. The film 22 and the layer 23 are oxidized selectively and the field film 26 is shaped, the nitride film 24, a poly Si layer 23' not oxidized and the oxide film 22 are successively etched and removed, and the element forming region is exposed. A memory cell having the capacity gate electrode 29 and a FET gate electrode 32 in two layer poly Si structure is prepared. Accordingly, a defect is not formed in the substrate 31, an extent (a bird-beak) in the lateral direction is minimized, and the separation oxide film 26 can be shaped while the capacity gate is molded being contacted with the overhang- shaped oxide film 26, thus preparing the dynamic RAM, which is integrated to a high degree, in high yield.

Inventors

  • 👤 Junichi Matsunaga
  • 👤 Hiroshi Nozawa
  • 👤 Hisahiro Matsukawa

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 16:34
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30

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