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JPS5789239A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor integrated circuit

Assignee: Seiko Epson Corp
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Filing: 1980-11-26
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Granted: —
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Expires: 2000-11-26
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Abstract

Abstract PURPOSE:To improve reliability by reducing interconnection resistance as well as improving integration density for semiconductor integrated circuits where more than one polysilicon layer is used for interconnection or as capacitor or resistor, and all the polysilicon layers are made to be N type. CONSTITUTION:After producing an oxidized silicon layer 11 and a polysilicon layer 12 on a silicon substrate 10, N<+> diffusion is made on the entire surface. Then, the N<+> polysilicon layer 12 is patterned in a specified shape by photolithographic etching process. After this, a second polysilicon layer is laminated on the CVD-SiO2 layer 13 under the same condition as the first layer after providing a contact hole on the layer 13. As the previous procedure, N<+> diffusion is made also on the second layer and the interconnection between two N<+> polysilicon layers is completed by forming the second layer in a specified shape. Such construction is most suited for high density assembly of semiconductor integrated circuit because of no connecting points due to no P-N junctions on polysilicon.

Inventors

  • 👤 Toshio Kano

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-30 03:53
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01

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