Semiconductor memory device

Abstract

Abstract PURPOSE:To reduce the area of a memory cell, by longitudinally and cubicly constituting a capacitor between a separation layer formed on a 1st conductor substrate and a 2nd conductor epitaxial region diffused below, and a diffusion layer connected to a transfer gate and a bit line. CONSTITUTION:An N<+> diffusion region 8 for a memory capacity is formed to extend as far as beneath a separation oxide film 2 on a P type semiconductor substrate 1. A P type region 9 and N<+> diffusion layer 10 are formed by epitaxial growth on the region 8. A poly-silicon layer for a transfer gate is connected to the layer 9 via a dielectric thin film 7. The P-N junction capacitance between the N<+> region 8 of a large area and the substrate acts as capacitor. This partial charge is controlled by an FET which holds the P type layer 9 and the poly- silicon layer 5 with the thin film layer 7. The N<+> layer 10 is connected to a bit line. This reduces a cell area and makes high-dense.

Inventors

• 👤 Takayuki Matsukawa
• 👤 Kyohiko Kotani

Bibliographic Details