High tension-resisting planer-type semiconductor device

Abstract

Abstract PURPOSE:To obtain the high tension-resisting planer-type device by forming deep a circular P-type layer to be positioned in the outermost part on one surface of an N-type Si substrate and by making the same contact with an N<+> layer on the other surface of the substrate. CONSTITUTION:The circular P-type layer 2a to be positioned in the outermost part on one surface of the N-type Si substrate 3 is formed deep and made to contact with the N-type layer 4 on the other surface of the substrate 3. In this structure, after a space-charge layer reaches from the main pn junction J to a guard ring JR, it further extends, with the increase in reversed bias, into the inside of the substrate and reaches a contact point Q' with the N<+> layer 4. Therefore, breakdown voltage inside the substrate is obtained and further an extremely-high breakdown voltage characteristic equalling the one of a mesa structure is obtained, while the leak current is little at the time of impression of high-temperature reverse voltage. In addition, the miniaturization of a chip can be achieved, since the circular layer 2a shows a voltage characteristic equivalent to the one of several guard rings.

Inventors

• 👤 Akimitsu Kawaguchi

Bibliographic Details