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JPS5769583A Expired / Lapsed JP ⏱️ 0.0 years remaining

Non_volatile semiconductor memory

Assignee: Toshiba Corp
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Filing: 1980-10-15
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Granted: —
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Expires: 2000-10-15
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Abstract

Abstract PURPOSE:To shorten a program time, by writing a data simultaneously in >=2 addresses of a memory area for obtaining a data of 1 bit. CONSTITUTION:IG-FET8A and 8B decide to write a data ''1'' or ''0'' in memory cells designated by a block A and B, respectively. In this case, a potential detecting circuit 9 decides an on or off state of the FETs 8A, 8B in accordance with a potential level of a supplied write data. In this case, a write data is written, for instance, by classifying it into 4 kinds of potential, and writing data of 2 addresses such as A0=''0'' and A0=''1'' by turning on and off the FETs 8A, 8B by the potential of outputs (s), (t) of the circuit 9, and 2 memory cells selected by a line decoder 5 and a row decoder 14 are programmed at the same time.

Inventors

  • 👤 Hiroshi Iwahashi
  • 👤 Masamichi Asano

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 17:31
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12; G11C16/32

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS54107638A Cited
JPS54110742A Cited

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