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JPS5754410A Expired / Lapsed JP ⏱️ 0.0 years remaining

Fet amplifying circuit

Assignee: Mitsubishi Electric Corp
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Filing: 1980-09-19
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Granted: —
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Expires: 2000-09-19
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Abstract

Abstract PURPOSE: To achieve excellent linearity, by connecting an amplifying circuit in which an input signal and its inversion signal are applied to two FETs of the same characteristics and the difference between the drain currents is picked up, and an amplifying circuit having constituents of opposite polarity complementarily and symmetrically for up and down. CONSTITUTION: An input Vi is inverted 2a with an FET 4a, and inverse characteristics are amplified 7a with an FET 8a, an FET 6a amplifier 5a positive transfer characteristics and applies it to an output circuit 9a to constitute the 1st FET amplifying circuit 14. Further, the 2nd FET amplifying circuit 15 having the same circuit constitution and the polarity of elements having the polarity entirely inversed, is provided to form circuits symmetrically up and down complementarily, and the inputs are connected and the mutual outputs are connected at point P 2 . With this constitution, no nonlinear element is included in an output signal and the linearity is excellent for the FET amplifier. COPYRIGHT: (C)1982,JPO&Japio

Inventors

  • 👤 Yoshio Uchiumi

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-23 12:56
CPC Classifications
—

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