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JPS5750307A Expired / Lapsed JP ⏱️ 0.0 years remaining

Time base correcting device

Assignee: Sony Corp
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Filing: 1980-09-05
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Granted: —
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Expires: 2000-09-05
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Abstract

Abstract PURPOSE: To perform the write control correctly, by adding a block address to every block of data and by using it for writing and checking. CONSTITUTION: A block address signal is inserted to a magnetic tape for every one block. A reproduced data WDT is supplied to a delay circuit 42 and a CRC checker 43, and output data WDT' from the circuit 42, a write control pulse WE' from an FF50 to which an error detection signal EDT is inputted from the checker 43, and an address from an address selector 44 are inputted to an RAM40 to output data RD. Data WDT' and a read block address RA are inputted to an ROM51, and a write block address WA is supplied to the selector 44. Input data is supplied to a memory 52 from a multiplexer 53, and an error flag EFLG is outputted through a latch 54. Thus, the write control is performed correctly. COPYRIGHT: (C)1982,JPO&Japio

Inventors

  • 👤 Takahiko Watanabe

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-06 05:24
CPC Classifications
G; G11; G11B; G11B5/00; G11B5/02; G11B5/09; G11B20/00; G11B20/10; G11B20/18; G11B20/1806; G11B20/1809; G11B20/10527; G11B5/027

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