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JPS5745752A Expired / Lapsed JP ⏱️ 0.0 years remaining

Line concentration multiplex circuit

Assignee: Hitachi Ltd
•
Filing: 1980-09-03
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Granted: —
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Expires: 2000-09-03
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Abstract

Abstract PURPOSE:To simultaneously perform parallel-serial conversion and serial-parallel conversion with one shift register, by providing a shift register having parallel input, parallel output, shift right and shift left and serial input operation mode functions and using it effectively. CONSTITUTION:A shift register 10 is constituted that it is in shift right mode when a terminal S1 is at a low potential L, and the data set in parallel with the output of a terminal QS is sequentially shifted. When it is shifted to time point of a CP-8, since a terminal S0 of the register 10 of a line concentration multiplex section 9 is at L and the terminal S1 is at H, the register 10 is shifted left by one bit at a pulse at the time point of CP-9. On the other hand, the data inputted from an outgoing highway 3 is fetched to a reception buffer from the parallel output terminals Q1-Q7 of the register 10 and the shift right serial input terminal SR at the point of time between the CP-8 and CP-9. At the point of time of the CP-9, since the terminal S0 of a line concentration multiplex section 9' is at H, the input data for terminals I1- I8 are set in parallel and shift-right is made to CP-16.

Inventors

  • 👤 Shiro Enami
  • 👤 Makoto Shinooka

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 06:39
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/45

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