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JPS574164A Expired / Lapsed JP ⏱️ 0.0 years remaining

Sos/mos transistor

Assignee: NEC Corp
•
Filing: 1980-06-09
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Granted: —
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Expires: 2000-06-09
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Abstract

Abstract PURPOSE:To work all original gate width as an effective gate by a method wherein the concentration of the impurities of the side and the lowermost section of an island-shaped Si layer just under the gate is made concentration, which is comparatively high and in which the desired threshold is obtained extending over the whole width of the surface. CONSTITUTION:A Si monocrystal film grown on a sapphire substrate 1 is mesa- etched and the island-shaped Si layer 2 is made up, the surface and the side of the layer 2 are coated with a gate oxide film 8 together and gate poly Si is placed on the oxide film. A region 7 of the lowermost section in the layer 2 is built up so that the concentration of impurities is comparatively high in order to decrease leak due to punch-through and back-channel. The regions 4 of the sides are regions having the high concentration of impurities formed in order to make the threshold of a side parasitic transistor TR higher than that of a surface TR, and the concentration of the impurities is approximately the same as the region 7. The concentration of the impurities of a region 9 of the surface is set properly conforming to the threshold, but the value is smaller than the region 7 or 4. There is no concentration difference of impurities in the lateral direction in a section under the gate oxide film functioning as the surface TR.

Inventors

  • 👤 Masao Fukuma

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-30 14:54
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS5286088A Cited
JPS5293277A Cited

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