← Back to Patent Explorer
JPS5740796A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor circuit

Assignee: NEC Corp
•
Filing: 1980-08-21
•
Granted: —
•
Expires: 2000-08-21
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE:To speed timing between input clocks by quickening the rising of an output by employing precharge timing which goes down to a low level immediately after a TTL level input clock is activated. CONSTITUTION:When a row strobe signal RAS changes from a high to a low level, a preseteing-precharging period changes into an activation period and an insulating gate type field effect transistor MOSTQ3 turns off. Then when an initial-stage output RAS rises up to a threshold voltage VDD level by bootstrap capacity C1F through a MOSTQ2, a contact 7 rises following up it through a MOSTQ18. Since an SE is grounded at this time, a MOSTQ20 is held turned off and a MOSTQ21 turns on, so that a contact 8 is grounded. Precharging timing PXO' comes after PXO by a MOSTQ22 and at the VDD level, but the MOSTQ22 turns off and a floating potential is held. Simultaneously with the MOSTQ21, an MOSTQ23 turns on and the PXO' goes down to the earth potential immediately.

Inventors

  • 👤 Akira Osami

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-30 08:05
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag