Instruction prefetching system

Abstract

Abstract PURPOSE:To enhance the processing speed, by prefetching the instruction of a branch destination in respect to a branch instruction designating an absolute or relative address. CONSTITUTION:A bit, which indicates whether a prefetched instruction held in a buffer 1 is the branch instruction of the absolute or relative address designation system or not, and a bit, which indicates information required for calculation of the address of the branch destination, out of bits constituting this prefetched instruction are inputted from the buffer 1 to an instruction prefetching address generating circuit 3 through a signal line D4. This instruction prefetching address generating circuit 3 generates the address of the branch destination if the branch instruction of the absolute or relative address designation system is held in the buffer 1, but otherwise, contents of a register 4 are increased by 1 simply. When the address of the branch destination is generated, this generation is reported to a register group 2 through a signal line C.

Inventors

• 👤 Etsuo Kusumoto

Bibliographic Details