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JPS57192079A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Hitachi Ltd
•
Filing: 1981-05-22
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Granted: —
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Expires: 2001-05-22
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Abstract

Abstract PURPOSE:To make a special wiring for short-circuit to be unnecessary at a semiconductor device by a method wherein a polycrystalline silicon layer of the lower layer is formed with the part converted into a P type and the part converted into an N type, and the upper layer is formed with a high melting point metal. CONSTITUTION:The P well 2 and field SiO2 films 3 for element isolation are formed on the main face of an N type silicon substrate 1, an N channel MISFET is provided on the P well 2, and a P channel MISFET is provided on the N type substrate 1. Gate electrodes 8-12 of the respective FET's and wirings thereof have two layers structure consisting of the lower layer of polycrystalline Si layer and the upper layer of molybdenum silicide layer, and the respective polycrystalline Si layer of the lower layer are consisting of the N<+> type polycrystalline Si layers 13, 14 and the P<+> type polycrystalline Si layers 17, 18. Accordingly the gate electrodes 9, 10 are connected by connection between the N<+> type polycrystalline Si layer 14 and the P<+> type polycrystalline Si layer 17 in the lower layer, and the molybdenum silicide layer 16 is in the common wiring condition in the upper layer.

Inventors

  • 👤 Shinji Shimizu

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-06 00:59
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/858

Claims Analysis

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References Cited (Backward Citations)

JPS5650535A Cited

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