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JPS5715455A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Fujitsu Ltd
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Filing: 1980-07-01
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Granted: —
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Expires: 2000-07-01
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Abstract

Abstract PURPOSE:To facilitate the evaluation of processing function and circuit function in a three-dimensional IC by forming a function inspecting monitor at each of element forming regions formed in a multilayer via insulating layers and exposing the measurement pad of the monitor. CONSTITUTION:Chips 1a-1c formed, for example, with MOSICs are covered with PSG film 5, are laminated with an adhesive layer 6 of silicone resin or the like, and are thus secured to form a three-dimensional LSI. A simple circuit function inspecting monitor circuit of flip-flop or the like and a processing function inspecting monitor element are formed in each of these chips, and their measuring pads 2, 3 are disposed similarly to the IC pad 4 at the peripheral edge of each of the chips. The chips are reduced in size smaller at the upper layer so that the respective pad forming regions are exposed on the surface of laminated three-dimensional device. Thus, the measurement inspection, e.g., function evaluation of each chip, influence of multilayer formation, variation in the performance by environmental tests or the like can be facilitated, the yield and the reliability can be improved.

Inventors

  • 👤 Junji Sakurai

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-23 13:03
CPC Classifications
H; H10; H10P; H10P74/00; H10W; H10W72/00; H10W72/90; H10W72/921; H10W72/926; H10W72/931; H10W72/932; H10W90/00; H10W90/701; H10W90/731; H10W90/732

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