Digital parallel adder

Abstract

Abstract PURPOSE:To contrive the increase in carrying speed, by optimizing the constitution of each partial adder, so that delays in a partial adder and those of signals successively propagated from a lower-rank adder may coincide with each other. CONSTITUTION:Carrying logical operation circuits 11, 12, 15, 16, 19, and 20 output a carry composed of an augend A, an addend B, and a carrying input CIN. Adders 13, 17, and 21 output a sum, S=A+B+C, from the augend A, the addend B, and the carrying input C. While the carry CIN changes over a selecting circuit 14, candidates C0<1> and C0<0> to be carried are obtained, and thus, a real carry C0 is decided effectively. While a candidate to be carried is successively decided as C1<1> C2<1> or C1<0> C2<0> in the second partial adding, the output of the lower-rank partial adder is decided in parallel as CIN C0, and those results are decided simultaneously as the output of COUT. When such arrangement is made, carrying signals can effectively be sent to the upper-rank adder two-demensinally, and therefore, high-speed operations can be made with a small circuit scale.

Inventors

• 👤 Takehiro Moriya
• 👤 Yukio Akazawa
• 👤 Atsushi Iwata

Bibliographic Details