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JPS5694574A Expired / Lapsed JP ⏱️ 0.0 years remaining

Complementary mos sense circuit

Assignee: Toshiba Corp
•
Filing: 1979-12-27
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Granted: —
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Expires: 1999-12-27
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Abstract

Abstract PURPOSE:To make high the speed of signal readout and to reduce the power consumption, by providing the FF in cross connection for the input and output terminals of two C-MOS inverters with an MOS transistor which prechanges FF into an intermediate potential before data input. CONSTITUTION:FF is constituted by cross connection of input and output terminals of the C-MOS inverter 13 consisting of p,n-channel MOS transistors (TR) 11, 12 and the inverter 16 consisting of similar transistors TR14, 15. At the power supply and ground side of FF, p,n-channel MOS TRs 17, 18 for FF activation inputting clock signals phi, inversion phi' to the gate are provided. Further, between the input terminals R1, R2 in common use of the output terminal of FF, a precharge use MOS TR19 with different conductive period as TRs 17, 18 and driven with the clock signal phi before the input to FF, is connected. Thus, since FF is precharged to the intermediate potential once at the power supply interruption prior to the data input, the response of output signal is quickened and low power consumption can be made.

Inventors

  • 👤 Mitsuo Isobe

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-06 20:12
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/065

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